The present invention generally relates to a direct memory access controller, and more particularly to a direct memory access controller capable of controlling a plurality of channels through which a direct memory access transfer is made.
Recently, it is required to transfer a large amount of data such as image data with extremely high speed between a data processing system such as a personal computer and a workstation, and an external unit such as a disk unit. It is also required to transfer a large amount of data between memories provided in the system at an extremely high speed. A conventional data transfer is carried out under the control of a central processing unit (hereafter simply referred to as CPU) provided in the data processing apparatus. Therefore, the process speed of the conventional data transfer depends on the processing speed of the CPU. From this viewpoint, it is impossible to transfer data at a speed in excess of the processing speed of the CPU. Further, it takes long to transfer a large amount of data even when the data is low-speed data. From the above-mentioned viewpoints, a direct memory access transfer is used which enables it to be possible to transfer data between the data processing system and the external unit without using the CPU. Hereafter, direct memory access is simply referred to as DMA. A DMA controller which controls the DMA transfer is intended to effectively process a large amount of data and high-speed data.
Generally, in the DMA controller, data is transferred in accordance with descriptors which are transfer control information necessary for the DMA transfer. Descriptors includes a source address, a destination address, and a byte count (the number of bytes of data to be transferred). In the conventional DMA transfer, a plurality of types of DMA transfer are proposed. Examples of those are a register direct mode, and a descriptor chain mode, which is further classified into a sequential descriptor chain mode and a link descriptor chain mode.
In the register direct mode, when a request for the DMA transfer occurs, the CPU releases a system bus from exclusive use, and then the DMA controller carries out the DMA transfer while exclusively using the system bus. At this time, various internal processing modes are processed in the DMA controller (this is called an internal process). For example, the DMA controller sets transfer control information which includes the source address, destination address and the byte count in internal registers. Then, after executing a predetermined error test, the DMA controller starts the data transfer based on the DMA transfer.
Generally, the DMA controller is provided with a plurality of channels in order to cope with a plurality of requests of the DMA transfer. A channel is defined as a path between a device and a memory, or a path between memories. For example, a four-channel DMA controller is a DMA controller such that data transfers through four paths are simultaneously controlled. For example, image data for use in CRT display is transferred through a channel, and other data is transferred through one of the other channels. Of course, a plurality of data transfers cannot be made with respect to the system bus at the same time. Therefore, when two or more data transfers are requested at the same time, data relating to each of the requested channels is segmented into a plurality of unit-length data, which are alternately transferred by switching the channels. Thereby, the data transfers through a plurality of channels are carried out as if they are executed at the same time. It can be seen from the above description that a reduction on channel switching time is very important to speed up the DMA transfer.
However, in the conventional DMA controller, the response to the request of the DMA transfer is slow, because the conventional DMA transfer starts the data transfer operation after the internal process is completed. For example, transfer control information is generated in response to each transfer request, and is set in the corresponding registers. Then the present channel is switched to the requested channel. Thereafter, the DMA transfer is started. Therefore, there occurs a delay in response time from the occurrence of the transfer request to the start thereof. It is to be noted that most of the response time is taken to carry out the internal process. Additionally, the internal process is included in the processing time of the DMA transfer irrespective of that the data transfer is not actually carried out during the internal process. Therefore, in the case where the channel switching is frequently carried out, time taken to perform the internal process increases as the number of channel switching operations increases. As a result, the DMA transfer processing time increases, which prevents speeding up of the DMA transfer. Particularly, the DMA transfer is intended to transfer an extremely amount of data for a short time. Consequently, it is required to reduce the response time for the DMA transfer request and speed up the entire data processing system.